In recent years, an Integrated Circuit (IC) is increasingly subject to the precision and purity of a semiconductor process as the dimension of the process shrinks and the complexity of the integrated circuit increases. The entire integrated circuit may not normally operate due to the deviation or defect of the process. In order to address this problem, more and more design companies of integrated circuits integrate electronic fuse (EFUSE) circuits available from a process factory (e.g., Taiwan Semiconductor Manufacturing Company (TSMC), and United Manufacturing Company (UMC)) into the integrated circuits to repair the deviation of the process or replace a defective circuit, thereby improving the yield of the integrated circuits.
An EFUSE circuit is composed of numerous electronic fuse units, each of which may be selectively blown by current. EFUSE circuits are widely applied in memory circuits, and when it is found that a defective cell exists in a memory circuit, a corresponding electronic fuse unit is blown by current, and the blown electronic fuse unit transmits such a signal that the deflective memory cell is replaced with a reserved normal memory cell to ensure normal operation of the entire memory circuit.
FIG. 1 illustrates a circuit of an electronic fuse unit including a conductive polysilicon electronic fuse 11, an N-type Metal Oxide Semiconductor (MOS) transistor 12 and an EFUSE status detection circuit 13. The polysilicon electronic fuse 11 has one terminal connected with a power source VFS and the other terminal connected with the drain 121 of the N-type metal oxide semiconductor transistor 12. The N-type metal oxide semiconductor transistor 12 has the source 122 grounded and the gate 123 connected with a programming control signal Vg. The EFUSE status detection circuit 13 has one terminal connected with the drain 121 of the N-type metal oxide semiconductor transistor 12 and the other terminal from which an EFUSE control signal is output. An IC controls a blown status of the polysilicon electronic fuse 11 by programming the voltage waveform of the programming control signal Vg. Without blowing the polysilicon electronic fuse 11, the programming control signal of Vg=0 is output, thus the N-type metal oxide semiconductor transistor 12 is turned off, and no current flows through the polysilicon electronic fuse 11 and the N-type metal oxide semiconductor transistor 12, so the polysilicon electronic fuse 11 will not be blown. Since the conductive polysilicon electronic fuse 11 is connected with the power source VFS, the drain 121 of the N-type metal oxide semiconductor transistor is in a low resistance status, the EFUSE status detection circuit 13 detects the low resistance status and outputs an EFUSE control signal of “1”. To make the EFUSE status detection circuit output an EFUSE control signal of “0”, the polysilicon electronic fuse 11 has to be blown. An operation principle thereof is as follows: the power source VFS is powered on so that the voltage of the power source VFS rises to a specific value, as illustrated in the voltage waveform of the power source VFS in FIG. 2; and after the power source VFS is powered on, the programming control signal Vg at a high level is output, as illustrated in the voltage waveform of the programming control signal Vg in FIG. 2. Since the programming control signal Vg is at a high level, the N-type metal oxide semiconductor transistor 12 is turned on and the polysilicon electronic fuse 11 is blown rapidly due to significant current flowing therethrough, and thereafter the programming control signal Vg at a low level is output and it is not necessary for the power source VFS to be at a high voltage. At this time the drain 121 of the N-type metal oxide semiconductor transistor is in a high resistance status and the EFUSE status detection circuit 13 detects the high resistance status and outputs the EFUSE control signal of “0”.
During programming, the voltage of the power source VFS has to be both above the lowest voltage VL in order to ensure sufficient power to blow the polysilicon electronic fuse 11 and below the highest voltage VH in order to prevent an excessive voltage thereof from blowing the N-type metal oxide semiconductor transistor 12, as illustrated in the dotted lines in FIG. 2. Typically, VL is at 3.8V and VH is at 4.2V. Furthermore, the voltage of the power source VFS is at zero or floats without programming, that is, the power source VFS satisfies the following conditions:
with programming: 3.8V<VFS<4.2V; and
without programming: at zero or floating.
However, there are conventional power sources of integrated circuits at 5V, 3.3V, 2.5V, 1.8V and 1.2V, thus an additional power supply circuit is required for an integrated circuit integrated with an EFUSE circuit to power the EFUSE circuit.
FIG. 3 illustrates a schematic diagram of a circuit for powering an integrated circuit integrated with an EFUSE circuit in the prior art, which includes an IC internal circuit and an IC external circuit. The IC internal circuit includes a programming power supply control circuit 31, an EFUSE circuit 32, an IC power supply circuit 33 and other functional circuits 34 of the IC. The IC external circuit includes a capacitor 35 and an EFUSE power supply circuit 36. Signals between the IC internal circuit and the IC external circuit are transferred through three pins 37, 38 and 39.
An operation principle of the circuit illustrated in FIG. 3 is as follows: the IC power supply circuit 33 generates a voltage VCC connected with the capacitor 35 through the pin 37 of the integrated circuit, and the capacitor 35 functions to regulate the voltage VCC (the capacitor 35 and the pin 37 may be dispensed if the voltage VCC is not required with high stability), and also the voltage VCC powers the other functional circuits 34 of the IC; and the programming power supply control circuit 31 generates a programming control signal and an EFUSE power supply control signal to control the EFUSE circuit 32 and the EFUSE power supply circuit 36 respectively, and the EFUSE power supply circuit 36 generates a voltage VFS to power the EFUSE circuit 32 through the pin 38 of the IC. To program the EFUSE circuit 32, the programming power supply control circuit 31 outputs a first EFUSE power supply control signal to the EFUSE power supply circuit 36 through the pin 39 to control the EFUSE power supply circuit 36 to generate and output the voltage VFS between 3.8V and 4.2V to the EFUSE circuit 32 so that an electronic fuse in the EFUSE circuit 32 may be normally programmed. After programming of the electronic fuse in the EFUSE circuit 32, the programming power supply control circuit 31 outputs a second EFUSE power supply control signal to the EFUSE power supply circuit 36 through the pin 39 to control the EFUSE power supply circuit 36 to output the voltage VFS at a low level or no voltage VFS where the voltage VFS is at zero or floats. After programming of the electronic fuse in the EFUSE circuit 32, the EFUSE circuit 32 outputs an EFUSE control signal to control the other function circuits 34 of the IC to perform desired functions.
As can be apparent from the foregoing description, the EFUSE power supply circuit 36, the pins 38 and 39 have to be added correspondingly for integrating the EFUSE circuit 32 in the integrated circuit, thus increasing the production and usage costs of the integrated circuit.